1. Field of the Invention
The present invention relates to a semiconductor memory device having a cross-point type of memory cell array in which memory cells are arranged in the row and column directions, each memory cell in the same row has one end connected to the same row selection line, and each memory cell in the same column has the other end connected to the same column selection line.
2. Description of the Related Art
Recently, development has been progressed for a cross-point type of semiconductor memory device (referred to as the cross-point memory hereinafter) which provides a memory cell array by connecting memory elements directly to a row selection line (referred to as the data line hereinafter) and to a column selection line (referred to as the bit line hereinafter) in the memory cells without providing a selection element other than the memory elements (refer to Japanese Unexamined Patent Publication No. 2002-8369, for example).
According to “method of detecting equal voltage for resistive cross-point memory cell array” disclosed in the Japanese Unexamined Patent Publication No. 2002-8369, a resistance state of a memory cell of a MRAM (Magnetic Random Access Memory) is detected by supplying a predetermined voltage to each data line and bit line. According to this document, when a selected memory cell is read, a first voltage is applied to the selected data line, and a second voltage lower than the first voltage is applied to the selected and non-selected bit lines and non-selected data lines to detect the resistance state, that is, a memory state of the selected memory cell.
FIG. 24 is a circuit diagram showing a memory cell array of a conventional cross-point memory and set levels and current paths of a supplied voltage to data lines and bit lines. According to the cross-point memory shown in FIG. 24, when the selected memory cell is read, a third voltage V2 is applied to a selected bit line, and a fourth voltage V1 higher than the third voltage V2 is applied to selected and non-selected data lines and non-selected bit lines to detect a resistance state of the selected memory cell.
FIG. 24 shows the case where the resistance state of the memory cell positioned at intersection of a data line D0 with a bit line B0 is determined by reading a current of the selected data line D0.
FIG. 25 shows voltage setting and a current path of each data line and each bit line when a resistance value of the memory cell at intersection of the data line D0 with the bit line B0 is read. Referring to FIG. 25, like the voltage setting in the above Japanese Unexamined Patent Publication No. 2002-8369, when a selected memory cell is read, a first voltage V1 is applied to a selected data line and a second voltage V2 lower than the first voltage V1 is applied to selected and non-selected bit lines and non-selected data lines to detect a resistance state of the selected memory cell. In this case, the resistance state of the desired memory cell is determined by reading a current of the bit line B0.
FIG. 26 shows current paths of leak currents Ileak0, Ileak1, . . . , Ileakk which are generated when a readout current Id of a memory cell Md is measured. Reference character M virtually designates an ampere meter which measures a current IM in the selected data line. In a readout state shown in FIG. 26, a voltage applied to the bit lines and data lines are set in the same manner shown in FIG. 24. In this case, a readout current Id of a memory cell Md is as shown by the following equation (1). In addition, a symbol of operation Σi=0˜k designates arithmetic sum in a range i=0˜k in this specification.Id=IM−Σi=0˜kIleaki  (1)
In addition, FIG. 27 shows current paths and directions of the leak currents Σi=0˜k Ileaki which are generated when a readout current Id1 of a memory cell Md1 is measured, and directions of the leak currents Σi=0˜k Ileak2i which are generated when a readout current Id2 of a memory cell Md2 is measured. In addition, in a readout state shown in FIG. 27, voltages applied to the bit lines and the data lines are set like in the case shown in FIG. 24. In this case, when a resistance value of the memory cell Md1 is low in the memory cells connected to the selected bit line, a voltage of a data line D1 drops because of voltage division corresponding to a resistance ratio between an on resistance value of a driver which drives the data line and a resistance value of the memory cell Md1.
Therefore, since the voltage of a d1A at intersection of the memory cell Md1 with the data line D1 is lower than the another data line voltage, a leak current which flows from each bit line to the memory cell Md1 is generated. That is, the leak current (passing through the non-selected memory cells) Σi=0˜k Ileak1i which flows from each bit line toward the memory cell Md1 through the data line D1 is generated. In this case, a relation between the readout current Id1 of the memory cell Md1 and a measurement current IM1 in the data line D1 is as shown by the following equation (2). Reference character M1 in FIG. 27 virtually designates an ampere meter which measures the current IM1.IM1=Id1−Σi=0˜kIleak1i  (2)
In addition, when a resistance value of the memory cell Md2 is high in the memory cells connected to the selected bit line, a voltage of the data line D2 rises because of voltage division corresponding to a resistance division ratio between the on resistance value of the driver which drives the data line and a resistance vale of the memory cell Md2.
Therefore, since the voltage of a d2A at intersection of the memory cell Md2 with the data line D2 is higher than the another data line voltage, a leak current (passing through the non-selected memory cells) Σi=0˜kIleak2i flows from the data line D2 toward each bit line. That is, the leak current Σi=0˜k Ileak2i which flows from the data line D2 toward a memory cell Mdx connected to each data line through each bit line is generated. In this case, a relation between the readout current Id2 of the memory cell Md2 and a measurement current IM2 in the data line D2 is as shown by the following equation (3). Reference character M2 in FIG. 27 virtually designates an ampere meter which measures the current IM2.IM2=Id2+Σi=0˜kIleak2i  (3)
The reason why the leak current is generated depending on the resistance value of the memory cell to be read is that a hypocritical resistance value exists in the data line and the bit line as shown in FIG. 28. More specifically, the hypocritical resistance value is a resistance value at the time of driving of drivers which drives the data line and the bit line.
FIG. 28 shows the case where voltages applied to the data lines and the bit lines are set in the same manner as in FIG. 24. First, as shown in FIG. 28, a driver A is necessary to set the voltage at the data line and the bit line. When this driver A is driven, on resistance is provided (assumed that the resistance value is R). When resistance values of the memory cells on the selected bit lines in the memory cell array such as R1, R2, R3 and R4 are different from each other, each voltage Vdi (i=1 to 4) of data lines 1 to 4 is shown by the following equation (4), where it is assumed that a driving voltage of each data line is V1 and a voltage on the selected bit line is V2′.Vdi=(V1−V2′)×Ri/(Ri+R)  (4)
As shown in the equation (4), as Ri is changed, the voltage Vdi of each data line is also changed. Therefore, the voltage of each data line fluctuates depending on the resistance value of the memory cells on the selected bit line, so that the leak current is generated.
Next, a case where the memory cell array is accessed (selected) by the bank will be described with reference to FIG. 29. FIG. 29 shows that the memory cell array is divided into a plurality of banks. In this case, in addition to the on resistance of the driver described with reference to FIG. 28, on resistance of a bank selection transistor BSi is added.
Therefore, voltage fluctuation of the data line becomes larger as compared with the case of the single memory cell array constitution shown in FIG. 28. When a memory cell is read in a memory cell array 10 (bank 1) shown in FIG. 29, it is necessary to turn on the transistor in a transistor column BS1 (bank selection transistor column) which selects the memory cell array 10 (bank 1). In addition, in order not to select other memory cell arrays MR0, MR2, and MR3 (banks 0, 2, and 3), it is necessary to turn off all of the transistors of the bank selection transistor columns BS0, BS2 and BS3. Thus, when the transistor in the bank selection transistor column BS1 is turned on, on resistances Rbs1, Rbs2, . . . , Rbsx of the transistors are provided on the data line. Therefore, a voltage Vdij of the data line in each bank shown in FIG. 29 is shown by the following equation (5), where reference character “i” designates an order of the data line in the same bank and “j” designates an order of the bank. In addition, reference character Rij designates a resistance value of the memory cell connected to the selection bit line and the i-th data line in the bank j.Vdij=(V1−V2′)×Rij/(Rij+R+Rbsj)  (5)
As shown in the equation (5), the voltage Vdij of the data line in each bank shown in FIG. 29 fluctuates larger than the voltage of the data line shown in the equation (4).
FIG. 30 shows an example of a data line driver-amplifier circuit shown in FIG. 28. The data line driver-amplifier circuit applies a predetermined voltage (power supply voltage Vcc, for example) to selected and non-selected data lines. A P-channel MOSFET (referred to as the PMOS hereinafter) (PO) in the data line driver-amplifier circuit supplies a drive current Ix which accesses a memory cell from the data line. When a resistance value of the accessed memory cell is great, since the current supplied from the PMOS (PO) of the data line drive circuit in FIG. 30 to the memory cell array is reduced, the gate voltage of the PMOS becomes high. Alternatively, when the resistance value of the accessed memory cell is small, since the current supplied from the PMOS (PO) to the memory cell array is increased, the gate voltage of the PMOS(PO) becomes low. The gate voltage of the PMOS (PO) is amplified by PMOS (P1) in a data line current amplification circuit and a load transistor (N-channel MOSFET) in FIG. 30 and an amplified voltage V0 is output.
FIG. 31 shows an example of the bit line drive circuit in FIG. 28. The bit line drive circuit comprises a load circuit P0 of a PMOS and a column selection circuit comprising two CMOS transfer gates. When a bit line is selected by a decode output of a column address decoder (column decoder), the column selection circuit turns on the right CMOS transfer gate in FIG. 31, and supplies a ground voltage Vss to the bit line and when the bit line is not selected, it turns on the left CMOS transfer gate in FIG. 31 and supplies a voltage which drops from the power supply voltage Vcc by a threshold voltage of the PMOS (P0). In addition, the voltage supplied to the bit line when the bit line is not selected is the same level as that supplied to the data line.
As described above, the current IM1 measured in the data line D1 in FIG. 27 is shown by the equation (2) and the current IM2 measured in the data line D2 in FIG. 27 is shown by the equation (3). As shown in the equations (2) and (3), when the predetermined voltage is applied to each of the data line and the bit line at the time of readout, using the conventional data line driver-amplfier circuit and the conventional bit line driver, the flowing direction of the leak current is changed depending on the resistance value of the memory cell to be read. Thus, when the leak current value is great, it becomes difficult to calculate the memory cell readout currents Id1 and Id2 from the currents IM1 and IM2 measured on the data lines.
As described above, FIG. 25 showed the set level of the voltage supplied to the data line and the bit line and its path at that time in “method of detecting equal voltage for resistive cross-point memory cell array” disclosed in Japanese Unexamined Patent Publication No. 2002-8369. In addition, FIG. 32 shows flowing directions of the leak currents when a resistance value of a selected memory cell is great, in a case where the voltage setting level shown in FIG. 25 is employed.
Referring to FIG. 32, when the resistance value of the selected memory cell is great, the direction of the memory cell current Id1 flowing in the bit line B0 is the same as the directions of the leak currents Ileak0, Ileak1, . . . Ileakk. Furthermore, as shown in FIG. 27, when the resistance value of the selected memory cell is small, the direction of the memory cell current Id2 flowing in the bit line B0 is opposite to the directions of the leak currents Ileak00, Ileak01, . . . Ileak0k. In this case, since the values of the measured currents IM1 and IM2 are greatly changed according to the leak current value, the memory cell currents Id1 and Id2 cannot be correctly detected. There is a problem in which the leak current flows back depending on the resistance value of the selected memory cell even with the method of setting the voltage supplied to the data line and the bit line in FIG. 31, similar to the leak current shown in FIGS. 32 and 33.